This invention relates in general to integrated circuit ("IC") test systems and in particular, to an IC test system readily adaptable to testing a variety of ICS having different power and ground bond pad configurations, or when packaged, different power and ground pin configurations.
Integrated circuits, especially those of the so-called application specific type, may have any one of a number of different power and ground bond pad and/or pin configurations. FIG. 1A illustrates, as a simplified example, a top plan view of one such IC die 100, wherein bond pads 1-16 provide external device electrical connection means to the active circuitry 50 of the IC die 100. Depending upon the functionality and layout of the active circuitry 50, some of the bond pads will be assigned by the layout designer to communicate input and/or output signals "S" to and/or from the active circuitry 50, at least one bond pad will be assigned to provide power "P" to the active circuitry 50, and at least one bond pad will be assigned to provide an external ground connection "G" to the active circuitry 50.
FIGS. 1B-1D illustrate examples of such possible bond pad assignments (also referred to herein as "bond pad configurations") for the IC die example of FIG. 1A. FIG. 1B illustrates one example where opposing corner bond pads 1 and 9 are assigned to be power "P" bond pads, opposing corner bond pads 5 and 13 are assigned to be ground "G" bond pads, and the remaining bond pads are assigned to be input and/or output signal "S" bond pads; FIG. 1C illustrates a second example where the power "P" and ground "G" bond pad assignments have been reversed; and FIG. 1D illustrates a third example where the power "P" and ground "G" bond pad assignments are not in the corner bond pads.
Similarly, for packaged integrated circuits, power and ground pin assignments may be different between various ICS, because of differences in their die layouts or differences in the board layouts wherein the packaged ICS are to be inserted. FIG. 2A illustrates, as a simplified example, a top plan view of a packaged IC 110 having pins 111-126 (shown as dotted circles) extending out of its bottom, and FIGS. 2B-2D illustrate examples of pin assignments for the packaged IC 110 of FIG. 2A.
FIG. 3 illustrates, as an example, a test system 700 for testing the packaged IC 110. Included in the test system 700 is an IC tester 400 having a plurality of test channels 6000 which provide test stimuli to and receive the resulting responses from the packaged IC 110 through connections connecting each of the pins 1-16 of the packaged IC 110 to a corresponding one of the test channels 6000 (e.g., pins 1-16 connected in sequential one-to-to correspondence with test channels 6001-6016 of test channels 6000, wherein pin 1 is connected to test channel 6001, pin 2 is connected to test channel 6002, and so on, to pin 16 which is connected to test channel 6016). Dotted line 412 illustrates the path of one such connection from pin 112 of the packaged IC 110 to the IC tester 400. Although not shown, similar connection paths to each of the remaining pins of the packaged IC 110 are also provided.
In practice, a number of mechanical structures are employed to electrically connect the pins of the packaged IC 110 to their respectively preassigned test channels 6001-6016. For example, the packaged IC 110 may be mounted onto an IC holder 172 (FIG. 4) having a plurality of contacts 131-146 which make electrical connections with respective pins 111-126 of the packaged IC 110 when mounted on the IC holder 172 (e.g., pins 1-16 making electrical connection in sequential one-to-one correspondence with contacts 131-146). The IC holder 172 is in turn, mounted on a device-under-test ("DUT") board 170 (FIG. 4) having a plurality of bottom contacts 151-166, wherein each of the bottom contacts 151-166 is electrically connected through conventional means to a respective one of the plurality of contacts 131-146 of the IC holder 172 (e.g., IC holder 172 contacts 131-146 making electrical connection in sequential one-to-one correspondence with DUT board 170 contacts 151-166).
The DUT board 170 is in turn, mounted on a load board 200 (FIGS. 5A and 5B), such that each of the bottom contacts 151-166 of the DUT board 170 makes electrical contact with a corresponding signal contact 251-266 formed on a top surface 202 (FIG. 5A) of the load board 200 (e.g., DUT board 170 contacts 151-166 making electrical connection in sequential one-to-one correspondence with load board 200 signal contacts 251-266). Electrically connected through conventional means to each of the top surface signal contacts 251-266 of the load board 200 is a corresponding bottom contact 281-296 formed on a bottom surface 204 (FIG. 5B) of the load board 200 (e.g., top surface signal contacts 251-266 making electrical connection in sequential one-to-one correspondence with bottom surface contacts 281-296).
The load board 200 is in turn, mounted on a test head 300, such that each of the bottom contacts 281-296 of the load board 200 makes electrical contact with corresponding contacts 311-326 (only 311 shown) formed on the test head 300 (e.g., load board 200 contacts 281-296 making electrical connection in sequential one-to-one correspondence with test head 300 contacts 311-326). Finally, the test head 300 contacts 311-326 are connected to corresponding ones of the test channels 6000 of the IC tester 400 through a cable 305 connected through connector 402 to the IC tester 400 (e.g., test head contacts 311-326 making electrical connection in sequential one-to-one correspondence with selected test channels 6001-6016 of the test channels 6000).
When power or ground connections are to be made to one of the pins of the packaged IC 110, instead of an input and/or output signal, the test channels connected to those selected pins are generally inactivated and means to switchably connect separate power and ground lines to those pins is required since the IC tester 400 does not supply enough current through its test channels 6000 for such power and ground connections. Where the load board 200 includes such means to switchably connect the separate power and ground lines to the power and ground pins, respectively, of the packaged IC 110, the separate power and ground lines (e.g., 601 and 602, respectively) may be provided to the load board 200 from the IC tester 400 via cable 305 which provides electrical signals from the IC tester 400 to the test head 300, and ribbon cable 280 which provides selected electrical signals from the test head 300 to the load board 200. In addition to providing connections to the power and ground lines 601 and 602, respectively, ribbon cable 280 may also provide additional electrical signals activating and/or controlling certain components performing the function on the load board 200 of switchably connecting the power and ground lines 601 and 602, respectively, to the power and ground pins of the packaged IC 110.
One example of a means of providing the power and ground lines 601 and 602, respectively, to the power and ground pins of the packaged IC 110 is to employ a dedicated load board for each specific power and ground bond pad and/or pin configuration. For example, instead of electrically connecting all of the pins of the packaged IC 110 to test channels, only pins dedicated to input and/or output signals would be electrically connected to selected test channels. Pins dedicated as power and ground pins would be electrically connected through conventional hardwiring techniques, for example, to their respective power and ground lines. The problem with such an approach, however, is that load boards are very expensive. Therefore, having a dedicated load board for each different power and ground bond pad or pin configuration is commercially impractical.
A more practical and therefore, commonly employed means of selectively connecting power or ground lines to any one of an integrated circuit's bond pads or pins is a so-called "killer board," a simplified example of which is depicted in FIGS. 5A and 5B, wherein FIG. 5A is a top plan view of the board and FIG. 5B is a bottom plan view. The "killer board" is a special type of load board which helps to connect each of the test channels to their assigned pins, and provides power or ground connections to the power and ground pins when the test channels of those pins are inactive. As schematically depicted in FIG. 6 for one test channel, each test channel is received by the "killer board" at an input contact (e.g., 281), which is internally connected by conventional means to both an output contact (e.g., 251) and an electrical relay (e.g., 211). The output contact (e.g., 251) of the "killer board" is in turn, connected to one of the pins of the packaged IC 110 under test, and the electrical relay (e.g., 211) is in turn, connected to an on-off-on switch or single-pole, triple throw ("SPTT") switch (e.g., 231) which is manually set to be connected to either the power line Vdd (e.g., 601), the ground line Vss (e.g., 602), or a no-contact position N/C.
Thereupon, when a particular test channel is to carry an input/output signal to the packaged IC 110 under test, its associated SPTT switch (e.g., 231) is manually set to the no-contact position N/C and/or its associated electrical relay (e.g., 211) is opened by an appropriate control signal to the relay's control input (e.g., C211). On the other hand, when the pin connected to the output contact (e.g., 251) of the "killer board" 140 is a power or ground pin, the test channel associated with that output contact (e.g., 251) is inactivated, the electrical relay (e.g., 211) associated with that output contact (e.g., 251) is closed by an appropriate signal to the relay's control input (e.g., C211), and the SPTT switch (e.g., 231) associated with that output contact (e.g., 251) is manually set to the appropriate power line Vdd (e.g., 601) or ground line Vss (e.g., 602) position.
Although the simplified "killer board" 200 depicted in FIGS. 5A and 5B only accommodates 16 test channels, it is to be appreciated that the example can be extended to higher and more practical numbers of test channels, such as for example, 256 test channels. Accordingly, as the number of test channels increase, the number of electrical relays and SPTT switches also increase proportionally, thus increasing the components cost of the "killer board" as well as increasing the complexity of its layout and as a result, board cost. In addition, as the number of test channels increase, the number of manual settings of the SPTT switches increase proportionally, thus increasing the set-up time and the likelihood that human error will cause errors in setting up the test configuration for each integrated circuit being tested.